1. Field of the Invention
The present invention relates to semiconductor technology using RESURF (reduced surface field) effect.
2. Description of the Background Art
As an example of technology for improving a breakdown voltage using RESURF effect is introduced in Japanese Patent Application Laid-Open No. 9-283716 (1997), which shows in FIG. 12 a semiconductor device comprising an n-channel RESURF MOSFET and a RESURF isolation island region. In this semiconductor device, an n− epitaxial layer 2 and an n+ buried diffusion region 4 are surrounded by a p diffusion region 3, whereby a RESURF structure is defined.
In the semiconductor device of FIG. 12 in Japanese Patent Application Laid-Open No. 9-283716 (1997), an aluminum interconnect line which experiences application of a high potential passes over the p diffusion region 3 placed at the same potential as a substrate potential. Extension of a depletion layer is thus inhibited by the electric field applied from the aluminum interconnect line 8, causing drop in breakdown voltage.
In response, Japanese Patent Application Laid-Open No. 9-283716 (1997) suggests in FIGS. 1 and 2 a semiconductor device which includes no RESURF structure between the n-channel RESURF MOSFET and the RESURF isolation island region. Instead, a narrow portion 1a as a part of a p− substrate 1 is formed therebetween which has an upper surface exposed from the p− substrate 1. When n diffusion regions 12a and 12b are subjected to application of a high potential, the portion 1a held between the n diffusion regions 12a and 12b are depleted, thereby causing no significant potential difference between the portion 1a and the n diffusion regions 12a, 12b. As a result, the potential difference is controlled to be small between the aluminum interconnect line 8 and the surface of the p− substrate 1 thereunder, whereby the foregoing problem is avoided.
Semiconductor technology using RESURF effect is also introduced in U.S. Pat. Nos. 4,292,642 and 5,801,418, and in “THIN LAYER HIGH-VOLTAGE DEVICES (RESURF DEVICES)”, pp. 1-13, J. A. Appels et al., Philips Journal of Research, vol. 35. No. 1, 1980, for example. Japanese Patent Application Laid-Open No. 5-190693 (1993) introduces a technique for stabilizing an electric field of a surface of a semiconductor substrate by means of capacitive coupling between field plates in a multilayered structure which are insulated from their surroundings. Japanese Patent Application Laid-Open No. 10-12607 (1998) introduces a technique for preventing generation of a leakage current by means of polarization of a molding resin.
In the semiconductor device of FIGS. 1 and 2 in Japanese Patent Application Laid-Open No. 9-283716 (1997), formation of the n diffusion regions 12a and 12b requires diffusion process for providing the portion 1a between the n diffusion regions 12a and 12b. That is, such a semiconductor device inherently experiences drop in surge breakdown voltage.